The present invention relates to a rework method for indium tin oxide (ITO) in a thin film transistor-liquid crystal display (TFT-LCD), and more particularly, to a rework method for Indium Tin Oxide in TFT-LCD, capable of reworking the point defect by re-depositing Indium Tin Oxide if a point defect is found in testing after depositing ITO used as a pixel electrode of a TFT-LCD.
FIG. 1 is a conventional unit pixel plan view showing a TFT-LCD. As shown therein, a gate line 2 and a data line 6 are arranged to cross with each other, and a pixel electrode 8, which is made using a transparent metal such as ITO, is disposed in a pixel area which is proximate the gate line 2 and the data line 6. A gate insulating film (not shown) is disposed between the gate line 2 and the data line 6 in order to insulate them electrically. A thin film transistor (TFT) is formed around an intersection of the gate line 2 and the data line 6 in order to control driving of a respective pixel.
The TFT includes a gate electrode 2A, which is a part of the gate line 2, the gate insulating film (not shown), which covers the gate electrode 2A, an active area formed on the gate insulating film as a pattern form, and a source electrode 6A and a drain electrode 6B formed on the active area to be apart a certain distance from each other. In addition, the drain electrode 6B is electrically connected to the pixel electrode 8 through a contact hole 9.
FIGS. 2A-2D are sectional views sequentially illustrating a method for fabricating a TFT taken along section line A-Axe2x80x2 of FIG. 1 according to the conventional art.
As a first step (FIG. 2A), a gate electrode 2A is formed on a glass substrate 1, and a gate insulating layer 3, an amorphous silicon 4, and an n+ amorphous silicon 5 having a high density n-type ions injected therein are sequentially formed thereon. Then, patterning of the n+ amorphous silicon 5 and the amorphous silicon 4 is done by a photolithography process to form an active region above the gate insulting layer 3 corresponding to the upper portion of the gate electrode 2A.
As a second step (FIG. 2B), a source 6A and a drain 6B are formed by depositing a metal on the upper surface of the above structure in FIG. 2A and then patterned to form respective portions separated by a certain distance from the center portion of the n+ amorphous silicon 5. The source and drain 6A, 6B extend over the end portions of the amorphous silicon 4 and the n+ amorphous silicon 5, and onto a portion of the gate insulating layer 3. Here, portions of the n+ amorphous silicon 5 exposed between the source and drain portion 6A, 6B, and an upper portion of the amorphous silicon 4 are etched to define a channel region.
As a third step (FIG. 2C), a passivation layer 7 is deposited onto the structure of FIG. 2B and a contact hole 9 is formed through a portion of the passivation layer 7 using a photolithography process to expose an upper portion of the drain 6B.
As a fourth step (FIG. 2D), an ITO electrode 8 is deposited onto the structure of FIG. 2C and then patterned to form a pixel being connected with the exposed drain 6B.
Hereinafter, the method for fabricating a TFT in accordance with the conventional art will be described in more detail.
First, as depicted in FIG. 2A, a metal is deposited onto the upper portion of the glass substrate 1, a photoresist is coated on the upper portion of the metal, the photoresist coated on the upper portion of the metal is exposed and developed to form a photoresist pattern. The gate electrode 2A is formed by etching the metal by an etching process using the photoresist pattern as an etching mask, and the photoresist pattern is removed. Then, the insulating layer 3, the amorphous silicon 4 and the n+ amorphous silicon 5 are sequentially deposited on the above structure. A photoresist is coated onto the upper surface of the n+ amorphous silicon 5, then exposed and developed to form a photoresist pattern at portions opposing the upper and surrounding areas of the gate electrode 2A. Next, an active region is formed at the upper and surrounding areas of the gate electrode 2A by patterning the n+ amorphous silicon 5 and the amorphous silicon 4 using an etching process employing the photoresist pattern as an etching mask, and the photoresist pattern is then removed using a wet etchant, etchant gas or the like.
As depicted in FIG. 2B, a metal is deposited onto the structure of FIG. 2A, and then a photoresist is coated thereon. After forming a photoresist pattern upon exposure and development, the metal is etched using an etching process employing the photoresist pattern as an etching mask to form a source 6A and a drain 6B being respectively separated by a certain distance above the center portion of the n+ amorphous silicon 5 and formed onto a portion of the gate insulating layer 3 at the sides of the active region.
The above etching process is continued so that portions of the n+ amorphous silicon 5 exposed between the source and drain 6A, 6B, and an upper portion of the amorphous silicon 4 under the n+ amorphous silicon 5 are etched to define a channel region.
Next, as depicted in FIG. 2C, the passivation layer 7 is deposited onto the upper surface of the structure of FIG. 2B, and an upper portion of the drain 6B is exposed by forming a contact hole 9 through the passivation layer 7 using a photolithography process.
Finally, as depicted in FIG. 2D, a pixel contacting the exposed drain 6B is formed by depositing an ITO electrode 8 at the upper surface of the structure of FIG. 2C and patterning thereof is performed by a photolithography process.
In the process of forming the ITO electrode 8, however, the ITO electrode 8 layer may be disconnected or disjointed between the drain 6 and the passivation layer 7 and by the slope of the contact hole 9.
FIG. 3 is an enlarged cross-sectional view of the structure at the upper side in FIG. 2D. As shown therein, the drain 6B positioned at the side portion and the upper side of the active region is formed as corresponding to the step of the active region. In addition, the upper surface of the passivation film 7, which is formed on the upper surface of the drain 6B, is also unevenly formed as corresponding to the step.
Since the contact hole 9 is formed on the passivation film 7 having the uneven upper surface and the ITO electrode 8 connected to the drain 6B through the contact hole 9 is formed, the opening on the ITO electrode 8 may occur at the side surface portion by the affect of the slope on the contact hole 9, and by the problems on the depositing process of the ITO electrode 8.
FIG. 4 is a cross-sectional view in the line B-Bxe2x80x2 direction of FIG. 1, showing a section of a capacitor that is a part for storing electric charge in driving pixels. In this case the ITO electrode 8 is opened by the step or a point defect. Therefore, an inferiority in driving the device occurs since the function of storing the electric charge cannot be performed by the ITO electrode 8.
Conventionally, when problems such as a point defect or an opening in the ITO electrode 8 occurred, the panel in which a problem occurred was discarded since it could not be used for further processes.
As described above, with the conventional fabrication method of the TFT-LCD, if a point defect or the like occurs in the ITO electrode, loss in cost and time could be prevented by disposing of the electrode for the further processes, since there is no rework method of the electrode, but the cost for the former process and time loss of the process cannot be restored.
Therefore, the present invention provides at least one method of fabricating a thin film transistor-liquid crystal display device. In one preferred embodiment of the invention, the method is achieved by providing a substrate having a plurality of pixels, forming a thin-film transistor in each of the plurality of pixels, depositing a passivation layer over the substrate, and forming a pixel electrode in each of the plurality of pixels.
In another preferred embodiment of the invention, the method is achieved by forming a gate electrode on a glass substrate, depositing an insulating film and amorphous silicon on a whole upper surface of the gate insulating film and the glass substrate and forming an active region by patterning the amorphous silicon; forming a source and drain, which are at a predetermined distance from each other on a center part of the active area and located on a side surface of the active area, by depositing metal on a whole upper surface of the active area and patterning the metal; forming a contact hole exposing an upper part of the drain by deposing a passivation film and patterning the passivation film; forming a first pixel electrode, which is connected to the exposed drain, on the passivation film by depositing an indium tin oxide (ITO) and patterning the ITO; forming a second pixel electrode by depositing an ITO and patterning the ITO.
The present invention further provides a thin film transistor-liquid crystal display device. In a preferred embodiment, the device includes at least a substrate having a plurality of pixels, a thin film transistor in each of the plurality of pixels, and a first pixel electrode formed in each of the plurality of pixels. The first pixel electrode is connected with a drain electrode of the thin film transistor. The thin film transistor includes a gate electrode and an insulating layer on the substrate, an active layer formed on the insulating layer, a source electrode and a drain electrode formed over the gate electrode and at opposing ends of the active layer, and a passivation layer exposing a part of the drain electrode.
The foregoing and other, features, aspects and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.